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VLSID
2002
IEEE
98views VLSI» more  VLSID 2002»
15 years 10 months ago
On Test Scheduling for Core-Based SOCs
We present a mathematical model for the problem of scheduling tests for core-based system-on-chip (SOC) VLSI designs. Given a set of tests for each core in the SOC and a set of te...
Sandeep Koranne
LCTRTS
2010
Springer
15 years 4 months ago
Versatile system-level memory-aware platform description approach for embedded MPSoCs
In this paper, we present a novel system modeling language which targets primarily the development of source-level multiprocessor memory aware optimizations. In contrast to previo...
Robert Pyka, Felipe Klein, Peter Marwedel, Stylian...
HICSS
2006
IEEE
131views Biometrics» more  HICSS 2006»
15 years 3 months ago
Design and Characterization of a Hardware Encryption Management Unit for Secure Computing Platforms
— Software protection is increasingly necessary for uses in commercial systems, digital content distributors, and military systems. The Secure Software (SecSoft) architecture is ...
Anthony J. Mahar, Peter M. Athanas, Stephen D. Cra...
NAR
2006
77views more  NAR 2006»
14 years 9 months ago
SMART 5: domains in the context of genomes and networks
The Simple Modular Architecture Research Tool 10 (SMART) is an online resource (http://smart.embl. de/) used for protein domain identification and the analysis of protein domain a...
Ivica Letunic, Richard R. Copley, Birgit Pils, Ste...
BMCBI
2008
115views more  BMCBI 2008»
14 years 9 months ago
BioGraphE: high-performance bionetwork analysis using the Biological Graph Environment
Background: Graphs and networks are common analysis representations for biological systems. Many traditional graph algorithms such as k-clique, k-coloring, and subgraph matching h...
George Chin Jr., Daniel G. Chavarría-Mirand...