49 search results - page 3 / 10 » A Trace-Driven Comparison of Algorithms for Parallel Prefetc... |
CCGRID
2010
IEEE
13 years 5 months ago
2010
IEEE
—While computing speed continues increasing rapidly, data-access technology is lagging behind. Data-access delay, not the processor speed, becomes the leading performance bottlen...
ISPDC
2010
IEEE
13 years 4 months ago
2010
IEEE
—Super-scalar, out-of-order processors that can have tens of read and write requests in the execution window place significant demands on Memory Level Parallelism (MLP). Multi- ...
ICDCS
2008
IEEE
14 years 21 days ago
2008
IEEE
The multi-level storage architecture has been widely adopted in servers and data centers. However, while prefetching has been shown as a crucial technique to exploit the sequentia...
IPPS
2005
IEEE
13 years 12 months ago
2005
IEEE
As technological process shrinks and clock rate increases, instruction caches can no longer be accessed in one cycle. Alternatives are implementing smaller caches (with higher mis...
IEEEPACT
2007
IEEE
14 years 17 days ago
2007
IEEE
We present a detailed characterization of instruction cache performance for IBM’s J2EE-enabled web server, WebSphere Application Server (WAS). When running two J2EE benchmarks o...