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» A Transactional Architecture for Simulation
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84
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ISCA
2000
IEEE
63views Hardware» more  ISCA 2000»
15 years 5 months ago
An embedded DRAM architecture for large-scale spatial-lattice computations
Spatial-lattice computations with finite-range interactions are an important class of easily parallelized computations. This class includes many simple and direct algorithms for ...
Norman Margolus
DAC
2002
ACM
16 years 1 months ago
Deriving a simulation input generator and a coverage metric from a formal specification
This paper presents novel uses of functional interface specifications for verifying RTL designs. We demonstrate how a simulation environment, a correctness checker, and a function...
Kanna Shimizu, David L. Dill
DAC
2003
ACM
16 years 1 months ago
Using a formal specification and a model checker to monitor and direct simulation
We describe a technique for verifying that a hardware design correctly implements a protocol-level formal specification. Simulation steps are translated to protocol state transiti...
Serdar Tasiran, Yuan Yu, Brannon Batson
151
Voted
DAC
2006
ACM
16 years 1 months ago
Symmetry detection for large Boolean functions using circuit representation, simulation, and satisfiability
- Classical two-variable symmetries play an important role in many EDA applications, ranging from logic synthesis to formal verification. This paper proposes a complete circuit-bas...
Jin S. Zhang, Alan Mishchenko, Robert K. Brayton, ...
99
Voted
VLSID
2002
IEEE
97views VLSI» more  VLSID 2002»
16 years 1 months ago
Multiple Faults: Modeling, Simulation and Test
We give an algorithm to model any given multiple stuck-at fault as a single stuck-at fault. The procedure requires insertion of at most ? ? ? modeling gates, when the multiplicity...
Yong Chang Kim, Vishwani D. Agrawal, Kewal K. Salu...