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107
Voted
RSP
2003
IEEE
103views Control Systems» more  RSP 2003»
15 years 6 months ago
An Instruction Throughput Model of Superscalar Processors
With advances in semiconductor technology, processors are becoming larger and more complex. Future processor designers will face an enormous design space, and must evaluate more a...
Tarek M. Taha, D. Scott Wills
104
Voted
IDA
2009
Springer
15 years 7 months ago
Selecting Computer Architectures by Means of Control-Flow-Graph Mining
Abstract Deciding which computer architecture provides the best performance for a certain program is an important problem in hardware design and benchmarking. While previous approa...
Frank Eichinger, Klemens Böhm
ISPASS
2005
IEEE
15 years 6 months ago
Studying Thermal Management for Graphics-Processor Architectures
We have previously presented Qsilver, a flexible simulation system for graphics architectures. In this paper we describe our extensions to this system, which we use— instrument...
Jeremy W. Sheaffer, Kevin Skadron, David P. Luebke
110
Voted
HPCC
2005
Springer
15 years 6 months ago
Memory Subsystem Characterization in a 16-Core Snoop-Based Chip-Multiprocessor Architecture
In this paper we present an exhaustive evaluation of the memory subsystem in a chip-multiprocessor (CMP) architecture composed of 16 cores. The characterization is performed making...
Francisco J. Villa, Manuel E. Acacio, José ...
GRID
2004
Springer
15 years 6 months ago
DIRAC: A Scalable Lightweight Architecture for High Throughput Computing
— DIRAC (Distributed Infrastructure with Remote Agent Control) has been developed by the CERN LHCb physics experiment to facilitate large scale simulation and user analysis tasks...
Andrei Tsaregorodtsev, Vincent Garonne, Ian Stokes...