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ICCAD
2002
IEEE
141views Hardware» more  ICCAD 2002»
15 years 9 months ago
A hierarchical modeling framework for on-chip communication architectures
— The communication sub-system of complex IC systems is increasingly critical for achieving system performance. Given this, it is important that the on-chip communication archite...
Xinping Zhu, Sharad Malik
CODES
2005
IEEE
15 years 6 months ago
Designing real-time H.264 decoders with dataflow architectures
High performance microprocessors are designed with generalpurpose applications in mind. When it comes to embedded applications, these architectures typically perform controlintens...
Youngsoo Kim, Suleyman Sair
VLSID
2007
IEEE
154views VLSI» more  VLSID 2007»
16 years 1 months ago
Model Based Test Generation for Microprocessor Architecture Validation
Functional validation of microprocessors is growing in complexity in current and future microprocessors. Traditionally, the different components (or validation collaterals) used i...
Sreekumar V. Kodakara, Deepak Mathaikutty, Ajit Di...
79
Voted
ICCAD
2005
IEEE
106views Hardware» more  ICCAD 2005»
15 years 9 months ago
FPGA device and architecture evaluation considering process variations
Process variations in nanometer technologies are becoming an important issue for cutting-edge FPGAs with a multimillion gate capacity. Considering both die-to-die and withindie va...
Ho-Yan Wong, Lerong Cheng, Yan Lin, Lei He
91
Voted
IPPS
2008
IEEE
15 years 7 months ago
Towards a decentralized architecture for optimization
We introduce a generic framework for the distributed execution of combinatorial optimization tasks. Instead of relying on custom hardware (like dedicated parallel machines or clus...
Marco Biazzini, Mauro Brunato, Alberto Montresor