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68
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ISCA
2008
IEEE
116views Hardware» more  ISCA 2008»
15 years 7 months ago
3D-Stacked Memory Architectures for Multi-core Processors
Three-dimensional integration enables stacking memory directly on top of a microprocessor, thereby significantly reducing wire delay between the two. Previous studies have examin...
Gabriel H. Loh
56
Voted
ITC
2003
IEEE
102views Hardware» more  ITC 2003»
15 years 6 months ago
CMOS Built-In Test Architecture for High-Speed Jitter Measurement
A BIST method measures accumulated jitter over N periods and requires no external references. Simulation using a 0.25um process shows a 625MHz - 1GHz input range with resolution o...
Henry C. Lin, Karen Taylor, Alan Chong, Eddie Chan...
97
Voted
ICANN
1997
Springer
15 years 5 months ago
On-Line Hebbian Learning for Spiking Neurons: Architecture of the Weight-Unit of NESPINN
: We present the implementation of on-line Hebbian learning for NESPINN, the Neurocomputer for the simulation of spiking neurons. In order to support various forms of Hebbian learn...
Ulrich Roth, Axel Jahnke, Heinrich Klar
ICC
2007
IEEE
15 years 4 months ago
A New Relaxation Labeling Architecture for Secure Localization in Sensor Networks
In this paper, a new strategy is proposed to defend against colluding malicious nodes in a sensor network. The new strategy is based on a new relaxation labeling algorithm to class...
Chih-Chieh Geoff Chang, Wesley E. Snyder, Cliff Wa...
117
Voted
EUROGP
2006
Springer
112views Optimization» more  EUROGP 2006»
15 years 4 months ago
The Halting Probability in Von Neumann Architectures
Abstract. Theoretical models of Turing complete linear genetic programming (GP) programs suggest the fraction of halting programs is vanishingly small. Convergence results proved f...
William B. Langdon, Riccardo Poli