Sciweavers

3955 search results - page 723 / 791
» A Transactional Architecture for Simulation
Sort
View
GLVLSI
2002
IEEE
108views VLSI» more  GLVLSI 2002»
15 years 4 months ago
Protected IP-core test generation
Design simplification is becoming necessary to respect the target time-to-market of SoCs, and this goal can be obtained by using predesigned IP-cores. However, their correct inte...
Alessandro Fin, Franco Fummi
ICS
2009
Tsinghua U.
15 years 4 months ago
A comprehensive power-performance model for NoCs with multi-flit channel buffers
Large Multi-Processor Systems-on-Chip use Networks-on-Chip with a high degree of reusability and scalability for message communication. Therefore, network infrastructure is a cruc...
Mohammad Arjomand, Hamid Sarbazi-Azad
ICES
2001
Springer
107views Hardware» more  ICES 2001»
15 years 4 months ago
Polymorphic Electronics
This paper introduces the concept of polymorphic electronics (polytronics) –referring to electronics with superimposed built-in functionality. A function change does not require ...
Adrian Stoica, Ricardo Salem Zebulum, Didier Keyme...
RT
2001
Springer
15 years 4 months ago
Real-Time High Dynamic Range Texture Mapping
This paper presents a technique for representing and displaying high dynamic-range texture maps (HDRTMs) using current graphics hardware. Dynamic range in real-world environments o...
Jonathan Cohen, Chris Tchou, Tim Hawkins, Paul E. ...
HPDC
2000
IEEE
15 years 4 months ago
Evaluation of Task Assignment Policies for Supercomputing Servers: The Case for Load Unbalancing and Fairness
While the MPP is still the most common architecture in supercomputer centers today, a simpler and cheaper machine configuration is growing increasingly common. This alternative s...
Bianca Schroeder, Mor Harchol-Balter