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» A Two-Phase Process for Software Architecture Improvement
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77
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VLSID
2002
IEEE
123views VLSI» more  VLSID 2002»
15 years 10 months ago
Compiler-Directed Array Interleaving for Reducing Energy in Multi-Bank Memories
With the increased use of embedded/portable devices such as smart cellular phones, pagers, PDAs, hand-held computers, and CD players, improving energy efficiency is becoming a cri...
Victor Delaluz, Mahmut T. Kandemir, Narayanan Vija...
70
Voted
ICAC
2007
IEEE
15 years 4 months ago
SLA Decomposition: Translating Service Level Objectives to System Level Thresholds
In today’s complex and highly dynamic computing environments, systems/services have to be constantly adjusted to meet Service Level Agreements (SLAs) and to improve resource uti...
Yuan Chen, Subu Iyer, Xue Liu, Dejan S. Milojicic,...
ICPP
2003
IEEE
15 years 2 months ago
Scheduling Algorithms with Bus Bandwidth Considerations for SMPs
The bus that connects processors to memory is known to be a major architectural bottleneck in SMPs. However, both software and scheduling policies for these systems generally focu...
Christos D. Antonopoulos, Dimitrios S. Nikolopoulo...
83
Voted
ECEH
2006
168views Healthcare» more  ECEH 2006»
14 years 11 months ago
Building a Smart Hospital using RFID Technologies
: Technologies of identification by radio frequencies (RFID) experience a fast development and healthcare is predicted to be one of its major growth areas. After briefly introducin...
Patrik Fuhrer, Dominique Guinard
ICS
2007
Tsinghua U.
15 years 3 months ago
Optimization and bottleneck analysis of network block I/O in commodity storage systems
Building commodity networked storage systems is an important architectural trend; Commodity servers hosting a moderate number of consumer-grade disks and interconnected with a hig...
Manolis Marazakis, Vassilis Papaefstathiou, Angelo...