74 search results - page 5 / 15 » A VHDL-based bus model for multi-PCB system design |
ICFEM
2005
Springer
15 years 3 months ago
2005
Springer
Abstract. Theorem provers, model checkers, static analyzers, test generators. . . all of these and many other kinds of formal methods tools can contribute to the analysis and devel...
BIRTHDAY
2006
Springer
15 years 1 months ago
2006
Springer
We describe a gate level design of a FlexRay-like bus interface. An electronic control unit (ECU) is obtained by integrating this interface into the design of the verified VAMP pro...
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WOTUG
2007
14 years 10 months ago
2007
Abstract. In this paper, we present a formal model and analysis of the AMBA Advanced High-performance Bus (AHB) on-chip bus. The model is given in CSP B—an integration of the pro...
ICCD
1995
IEEE
15 years 1 months ago
1995
IEEE
Symbolic model checking is a successful technique for checking properties of large finite-state systems. This method has been used to verify a number of real-world hardware desig...
TECS
2008
14 years 9 months ago
2008
tion. Transaction Level Modeling (TLM) has been proposed to abstract communication for highspeed system simulation and rapid design space exploration. Although being widely accepte...