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» A VHDL-based bus model for multi-PCB system design
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104
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MEMOCODE
2003
IEEE
15 years 4 months ago
LOTOS Code Generation for Model Checking of STBus Based SoC: the STBus interconnect
In the design process of SoC (System on Chip), validation is one of the most critical and costly activity. The main problem for industrial companies like STMicroelectronics, stand...
Pierre Wodey, Geoffrey Camarroque, Fabrice Baray, ...
DAC
2007
ACM
15 years 3 months ago
Performance Analysis of FlexRay-based ECU Networks
It is now widely believed that FlexRay will emerge as the predominant protocol for in-vehicle automotive communication systems. As a result, there has been a lot of recent interes...
Andrei Hagiescu, Unmesh D. Bordoloi, Samarjit Chak...
80
Voted
HYBRID
2009
Springer
15 years 3 months ago
Specification and Analysis of Network Resource Requirements of Control Systems
We focus on control systems in which sensors send data to actuators via a bus shared with other applications. An approach is proposed for specifying and implementing dynamic schedu...
Gera Weiss, Sebastian Fischmeister, Madhukar Anand...
84
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CAEPIA
2003
Springer
15 years 4 months ago
Towards a Generic Multiagent Model for Decision Support: Two Case Studies
This paper describes how agent and knowledge technology can be used to build advanced software systems that support operational decisionn complex domains. In particular, we present...
Sascha Ossowski, José-Luis Pérez-de-...
LCTRTS
2007
Springer
15 years 5 months ago
Interface synthesis for heterogeneous multi-core systems from transaction level models
This paper presents a tool for automatic synthesis of RTL interfaces for heterogeneous MPSoC from transaction level models (TLMs). The tool captures the communication parameters i...
Hansu Cho, Samar Abdi, Daniel Gajski