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» A Visual Approach to Validating System Level Designs
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VMCAI
2009
Springer
15 years 10 months ago
A Scalable Memory Model for Low-Level Code
Abstract. Because of its critical importance underlying all other software, lowlevel system software is among the most important targets for formal verification. Low-level systems...
Zvonimir Rakamaric, Alan J. Hu
DATE
2005
IEEE
164views Hardware» more  DATE 2005»
15 years 9 months ago
Automated Synthesis of Assertion Monitors using Visual Specifications
Automated synthesis of monitors from high-level properties plays a significant role in assertion-based verification. We present here a methodology to synthesize assertion monitors...
Ambar A. Gadkari, S. Ramesh
135
Voted
TSE
2002
119views more  TSE 2002»
15 years 3 months ago
Testing Homogeneous Spreadsheet Grids with the "What You See Is What You Test" Methodology
Although there has been recent research into ways to design environments that enable end users to create their own programs, little attention has been given to helping these end u...
Margaret M. Burnett, Andrei Sheretov, Bing Ren, Gr...
CODES
2005
IEEE
15 years 9 months ago
Automatic network generation for system-on-chip communication design
With growing system complexities, system-level communication design is becoming increasingly important and advanced, network-oriented communication architectures become necessary....
Dongwan Shin, Andreas Gerstlauer, Rainer Döme...
155
Voted
ANSS
2007
IEEE
15 years 9 months ago
Evaluating the Design of Biological Cells Using a Computer Workbench
For embedded systems as well as for biological cell systems, design is a feature that defines their identity. The assembly of different components in designs of both systems can ...
Tessa E. Pronk, Simon Polstra, Andy D. Pimentel, T...