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» A Visual Approach to Validating System Level Designs
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CCS
2009
ACM
15 years 8 months ago
On voting machine design for verification and testability
We present an approach for the design and analysis of an electronic voting machine based on a novel combination of formal verification and systematic testing. The system was desig...
Cynthia Sturton, Susmit Jha, Sanjit A. Seshia, Dav...
DAC
2006
ACM
16 years 5 months ago
Generation of yield-aware Pareto surfaces for hierarchical circuit design space exploration
Pareto surfaces in the performance space determine the range of feasible performance values for a circuit topology in a given technology. We present a non-dominated sorting based ...
Saurabh K. Tiwary, Pragati K. Tiwary, Rob A. Ruten...
134
Voted
IWQOS
2004
Springer
15 years 9 months ago
Topology design for service overlay networks with bandwidth guarantees
— The Internet still lacks adequate support for QoS applications with real-time requirements. In great part, this is due to the fact that provisioning of end-to-end QoS to trafï¬...
S. L. Vieira, Jörg Liebeherr
DBSEC
2004
170views Database» more  DBSEC 2004»
15 years 5 months ago
RBAC/MAC Security Analysis and Design for UML
In software construction, analysis investigates the boundary of a system (scope and requirements), its usage and access, and from a security perspective, who needs access to what ...
Thuong Doan, Steven A. Demurjian, Charles E. Phill...
DSD
2002
IEEE
110views Hardware» more  DSD 2002»
15 years 9 months ago
A Design for a Low-Power Digital Matched Filter Applicable to W-CDMA
This paper presents a design for a low-power digital matched filter (DMF) applicable to Wideband-Code Division Multiple Access (W-CDMA), which is a Direct-Sequence Spread-Spectrum...
Shoji Goto, Takashi Yamada, Norihisa Takayarna, Yo...