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» A Visual Approach to Validating System Level Designs
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CEC
2009
IEEE
15 years 10 months ago
Gate-level optimization of polymorphic circuits using Cartesian Genetic Programming
— Polymorphic digital circuits contain ordinary and polymorphic gates. In the past, Cartesian Genetic Programming (CGP) has been applied to synthesize polymorphic circuits at the...
Zbysek Gajda, Lukás Sekanina
ISVLSI
2007
IEEE
131views VLSI» more  ISVLSI 2007»
15 years 9 months ago
Improving the Quality of Bounded Model Checking by Means of Coverage Estimation
Formal verification has become an important step in circuit and system design. A prominent technique is Bounded Model Checking (BMC) which is widely used in industry. In BMC it i...
Ulrich Kühne, Daniel Große, Rolf Drechs...
164
Voted
MOBIHOC
2008
ACM
16 years 3 months ago
Collaborative query processing among heterogeneous sensor networks
Demands on better interacting with physical world require an effective and comprehensive collaboration mechanism among multiple heterogeneous sensor networks. Previous works mainl...
Yuan He, Mo Li, Yunhao Liu
ICRA
2002
IEEE
116views Robotics» more  ICRA 2002»
15 years 8 months ago
Staying Alive: A Docking Station for Autonomous Robot Recharging
—Autonomous mobile robots are constrained in their long-term functionality due to a limited on-board power supply. Typically, rechargeable batteries are utilized that may only pr...
Milo C. Silverman, Dan Nies, Boyoon Jung, Gaurav S...
DATE
2004
IEEE
143views Hardware» more  DATE 2004»
15 years 7 months ago
Fault-Tolerant Deployment of Embedded Software for Cost-Sensitive Real-Time Feedback-Control Applications
Designing cost-sensitive real-time control systems for safetycritical applications requires a careful analysis of the cost/coverage trade-offs of fault-tolerant solutions. This fu...
Claudio Pinello, Luca P. Carloni, Alberto L. Sangi...