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» A Visual Approach to Validating System Level Designs
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INFOVIS
2005
IEEE
15 years 8 months ago
Turning the Bucket of Text into a Pipe
Many visual analysis tools operate on a fixed set of data. However, professional information analysts follow issues over a period of time and need to be able to easily add new doc...
Elizabeth G. Hetzler, Vernon L. Crow, Deborah A. P...
ISQED
2006
IEEE
118views Hardware» more  ISQED 2006»
15 years 9 months ago
Language-Based High Level Transaction Extraction on On-chip Buses
Abstract— With the increasing in silicon densities, SoC designs are the stream in modern electronics systems. Accordingly, the verification for SoC designs is crucial. One of th...
Yi-Le Huang, Chun-Yao Wang, Richard Yeh, Shih-Chie...
ICCD
2005
IEEE
159views Hardware» more  ICCD 2005»
15 years 8 months ago
Architectural-Level Fault Tolerant Computation in Nanoelectronic Processors
Nanoelectronic devices are expected to have extremely high and variable fault rates; thus future processor architectures based on these unreliable devices need to be built with fa...
Wenjing Rao, Alex Orailoglu, Ramesh Karri
SEDE
2007
15 years 4 months ago
Case study: A tool centric approach for fault avoidance in microchip designs
— Achieving reliability in fault tolerant systems requires both avoidance and redundancy. This study focuses on avoidance as it pertains to the design of microchips. The lifecycl...
Clemente Izurieta
VISUALIZATION
1994
IEEE
15 years 7 months ago
Parallel Performance Measures for Volume Ray Casting
We describe a technique for achieving fast volume ray casting on parallel machines, using a load balancing scheme and an e cient pipelined approach to compositing. We propose a ne...
Cláudio T. Silva, Arie E. Kaufman