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» A Web-Based P Systems Simulator and Its Parallelization
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FDL
2003
IEEE
15 years 2 months ago
Object-Oriented ASIP Design and Synthesis
SystemC-Plus from the ODETTE project provides the ability to simulate and synthesise object-oriented specifications into hardware. The current ODETTE compiler translates each obj...
Maziar Goudarzi, Shaahin Hessabi, Alan Mycroft
JSA
2000
116views more  JSA 2000»
14 years 9 months ago
Distributed vector architectures
Integrating processors and main memory is a promising approach to increase system performance. Such integration provides very high memory bandwidth that can be exploited efficientl...
Stefanos Kaxiras
PERCOM
2009
ACM
15 years 4 months ago
On the Accuracy of RFID-based Localization in a Mobile Wireless Network Testbed
Abstract—The extensive recent research in protocols development for wireless networks must be complemented with simple yet efficient prototyping and evaluation mechanism. MiNT-2...
Vikram P. Munishwar, Shailendra Singh 0003, Xiaosh...
ISLPED
2003
ACM
122views Hardware» more  ISLPED 2003»
15 years 2 months ago
A mixed-clock issue queue design for globally asynchronous, locally synchronous processor cores
Ever shrinking device sizes and innovative micro-architectural and circuit design techniques have made it possible to have multi-million transistor systems running at multi-gigahe...
Venkata Syam P. Rapaka, Diana Marculescu
ISCA
2002
IEEE
105views Hardware» more  ISCA 2002»
15 years 2 months ago
Tarantula: A Vector Extension to the Alpha Architecture
Tarantula is an aggressive floating point machine targeted at technical, scientific and bioinformatics workloads, originally planned as a follow-on candidate to the EV8 processo...
Roger Espasa, Federico Ardanaz, Julio Gago, Roger ...