228 search results - page 27 / 46 » A bipartition-codec architecture to reduce power in pipeline... |
DAC
2001
ACM
15 years 10 months ago
2001
ACM
We highlight several fundamental challenges to designing highperformance integrated circuits in nanometer-scale technologies (i.e. drawn feature sizes < 100 nm). Dynamic power ...
78
Voted
HPCA
2006
IEEE
15 years 10 months ago
2006
IEEE
This paper explores the multi-dimensional design space for chip multiprocessors, exploring the inter-related variables of core count, pipeline depth, superscalar width, L2 cache s...
78
Voted
TC
2008
14 years 9 months ago
2008
This paper describes a new on-demand wake-up prediction policy for reducing leakage power. The key insight is that branch prediction can be used to selectively wake up only the nee...
EGH
2004
Springer
15 years 3 months ago
2004
Springer
The real time 3D graphics becomes one of the attractive applications for 3G wireless terminals although their battery lifetime and memory bandwidth limit the system resources for ...
95
Voted
TVLSI
2008
14 years 9 months ago
2008
This paper describes Glitchless, a circuit-level technique for reducing power in FPGAs by eliminating unnecessary logic transitions called glitches. This is done by adding program...