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» A case for FAME: FPGA architecture model execution
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NIXDORF
1992
116views Hardware» more  NIXDORF 1992»
15 years 1 months ago
Programmable Active Memories: A Performance Assessment
We present some quantitative performance measurements for the computing power of Programmable Active Memories (PAM), as introduced by [2]. Based on Field Programmable Gate Array (...
Patrice Bertin, Didier Roncin, Jean Vuillemin
CJ
2004
141views more  CJ 2004»
14 years 9 months ago
Modeling and Analysis of a Scheduled Maintenance System: a DSPN Approach
This paper describes a way to manage the modeling and analysis of Scheduled Maintenance Systems (SMS) within an analytically tractable context. We chose a significant case study h...
Andrea Bondavalli, Roberto Filippini
SIGSOFT
2001
ACM
15 years 10 months ago
An architecture for flexible, evolvable process-driven user-guidance environments
Complex toolsets can be difficult to use. User interfaces can help by guiding users through the alternative choices that might be possible at any given time, but this tends to loc...
Timothy J. Sliski, Matthew P. Billmers, Lori A. Cl...
COOPIS
2004
IEEE
15 years 1 months ago
A Distributed and Parallel Component Architecture for Stream-Oriented Applications
Abstract. This paper introduces ThreadMill - a distributed and parallel component architecture for applications that process large volumes of streamed (time-sequenced) data, such a...
Paulo Barthelmess, Clarence A. Ellis
ASAP
2005
IEEE
169views Hardware» more  ASAP 2005»
15 years 3 months ago
Alleviating the Data Memory Bandwidth Bottleneck in Coarse-Grained Reconfigurable Arrays
It is widely known that parallel operation execution in multiprocessor systems generates a respective increase in memory accesses. Since the memory and bus subsystems provide a li...
Grigoris Dimitroulakos, Michalis D. Galanis, Costa...