Sciweavers

159 search results - page 23 / 32
» A case for FAME: FPGA architecture model execution
Sort
View
102
Voted
CF
2006
ACM
15 years 3 months ago
Dynamic thread assignment on heterogeneous multiprocessor architectures
In a multi-programmed computing environment, threads of execution exhibit different runtime characteristics and hardware resource requirements. Not only do the behaviors of distin...
Michela Becchi, Patrick Crowley
WSC
2007
14 years 12 months ago
Conceptual modeling of information exchange requirements based on ontological means
Unambiguous definition of the information exchanged between distributed systems is a necessary requirement for simulation system interoperability. The ontological spectrum categor...
Andreas Tolk, Charles D. Turnitsa
WEBDB
2010
Springer
224views Database» more  WEBDB 2010»
15 years 2 months ago
Concurrent One-Way Protocols in Around-the-Clock Social Networks
We introduce and study concurrent One-Way Protocols in social networks. The model is motivated by the rise of online social networks and the fast development of automation feature...
Royi Ronen, Oded Shmueli
DATE
2011
IEEE
223views Hardware» more  DATE 2011»
14 years 1 months ago
Towards a Time-predictable Dual-Issue Microprocessor: The Patmos Approach
Current processors are optimized for average case performance, often leading to a high worst-case execution time (WCET). Many architectural features that increase the average case...
Martin Schoeberl, Pascal Schleuniger, Wolfgang Puf...
DAC
2012
ACM
13 years 1 days ago
WCET-centric partial instruction cache locking
Caches play an important role in embedded systems by bridging the performance gap between high speed processors and slow memory. At the same time, caches introduce imprecision in ...
Huping Ding, Yun Liang, Tulika Mitra