183 search results - page 31 / 37 » A case for multi-level main memory |
142
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CORR
2011
Springer
2011
Springer
On a linear programming approach to the discrete Willmore boundary value problem and generalizations
14 years 6 months ago
We consider the problem of finding (possibly non connected) discrete surfaces spanning a finite set of discrete boundary curves in the three-dimensional space and minimizing (glo...
203
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GLVLSI
2011
IEEE
14 years 3 months ago
2011
IEEE
This paper proposes a novel L1 data cache design with dualversioning SRAM cells (dvSRAM) for chip multi-processors (CMP) that implement optimistic concurrency proposals. In this n...
102
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SPAA
2004
ACM
15 years 5 months ago
2004
ACM
We present the Buffer Heap (BH), a cache-oblivious priority queue that supports Delete-Min, Delete, and Decrease-Key operations in O( 1 B log2 N B ) amortized block transfers fro...
CVPR
2005
IEEE
16 years 1 months ago
2005
IEEE
We present a novel multilinear algebra based approach for reduced dimensionality representation of image ensembles. We treat an image as a matrix, instead of a vector as in tradit...
CF
2009
ACM
15 years 6 months ago
2009
ACM
Resource management on accelerator based systems is complicated by the disjoint nature of the main CPU and accelerator, which involves separate memory hierarhcies, different degr...