Sciweavers

183 search results - page 32 / 37
» A case for multi-level main memory
Sort
View
ECRTS
2006
IEEE
15 years 5 months ago
WCET-Centric Software-controlled Instruction Caches for Hard Real-Time Systems
Cache memories have been extensively used to bridge the gap between high speed processors and relatively slower main memories. However, they are sources of predictability problems...
Isabelle Puaut
GLVLSI
2010
IEEE
164views VLSI» more  GLVLSI 2010»
15 years 4 months ago
Performance and energy trade-offs analysis of L2 on-chip cache architectures for embedded MPSoCs
On-chip memory organization is one of the most important aspects that can influence the overall system behavior in multiprocessor systems. Following the trend set by high-perform...
Mohamed M. Sabry, Martino Ruggiero, Pablo Garcia D...
EMSOFT
2009
Springer
15 years 4 months ago
Serving embedded content via web applications: model, design and experimentation
Embedded systems such as smart cards or sensors are now widespread, but are often closed systems, only accessed via dedicated terminals. A new trend consists in embedding Web serv...
Simon Duquennoy, Gilles Grimaud, Jean-Jacques Vand...
CAV
1992
Springer
96views Hardware» more  CAV 1992»
15 years 3 months ago
State-Space Caching Revisited
State-space caching is a veri cation technique for nite-state concurrent systems. It performs an exhaustive exploration of the state space of the system being checked while storin...
Patrice Godefroid, Gerard J. Holzmann, Didier Piro...
LCTRTS
2000
Springer
15 years 3 months ago
An Integrated Push/Pull Buffer Management Method in Multimedia Communication Environments
Multimedia communication systems require not only high-performance computer hardware and highspeed networks, but also a buffer management mechanism to process voluminous data effi...
Sungyoung Lee, Hyonwoo Seung, Taewoong Jeon