Sciweavers

183 search results - page 4 / 37
» A case for multi-level main memory
Sort
View
ISCA
1996
IEEE
120views Hardware» more  ISCA 1996»
15 years 1 months ago
Missing the Memory Wall: The Case for Processor/Memory Integration
Current high performance computer systems use complex, large superscalar CPUs that interface to the main memory through a hierarchy of caches and interconnect systems. These CPU-c...
Ashley Saulsbury, Fong Pong, Andreas Nowatzyk
HIPEAC
2011
Springer
13 years 9 months ago
Decoupled zero-compressed memory
For each computer system generation, there are always applications or workloads for which the main memory size is the major limitation. On the other hand, in many cases, one could...
Julien Dusser, André Seznec
75
Voted
ASPLOS
2012
ACM
13 years 5 months ago
A case for unlimited watchpoints
Numerous tools have been proposed to help developers fix software errors and inefficiencies. Widely-used techniques such as memory checking suffer from overheads that limit thei...
Joseph L. Greathouse, Hongyi Xin, Yixin Luo, Todd ...
FLAIRS
2003
14 years 11 months ago
Hybrid Deletion Policies for Case Base Maintenance
Case memory maintenance in a Case-Based Reasoning system is important for two main reasons: (1) to control the case memory size; (2) to reduce irrelevant and redundant instances t...
Maria Salamó, Elisabet Golobardes
SEUS
2009
IEEE
15 years 4 months ago
A Single-Path Chip-Multiprocessor System
Abstract. In this paper we explore the combination of a time-predictable chipmultiprocessor system with the single-path programming paradigm. Time-sliced arbitration of the main me...
Martin Schoeberl, Peter P. Puschner, Raimund Kirne...