121 search results - page 23 / 25 » A cell-based power estimation in CMOS combinational circuits |
ASPDAC
1999
ACM
13 years 10 months ago
1999
ACM
: In VLSI circuits with deep sub-micron, the parasitic capacitance from interconnect is a very important factor determining circuit performances such as power and time-delay. The B...
CODES
2003
IEEE
13 years 11 months ago
2003
IEEE
In this paper, we describe a new methodology based on game theory for minimizing the average power of a circuit during scheduling in behavioral synthesis. The problem of schedulin...
TVLSI
2008
13 years 6 months ago
2008
Applications in computer networks often require high throughput access to large data structures for lookup and classification. While advanced algorithms exist to speed these search...
ISLPED
2003
ACM
13 years 11 months ago
2003
ACM
Power will be the key limiter to system scalability as interconnection networks take up an increasingly significant portion of system power. In this paper, we propose an architec...
DAC
2010
ACM
13 years 6 months ago
2010
ACM
Many DTM schemes rely heavily on the accurate knowledge of the chip's dynamic thermal state to make optimal performance/ temperature trade-off decisions. This information is ...