1008 search results - page 2 / 202 » A cis-regulatory logic simulator |
ISMVL
2010
IEEE
14 years 10 months ago
2010
IEEE
ENTCS
2002
14 years 11 months ago
2002
Meseguer's rewriting logic and the rewriting logic CRWL are two well-known approaches to rewriting as logical deduction that, despite some clear similarities, were designed w...
DAC
2012
ACM
13 years 2 months ago
2012
ACM
Unknown values (Xs) may exist in a design due to uninitialized registers or blocks that are powered down. Due to X-pessimism in gate-level logic simulation, such Xs cannot be hand...
TCAD
1998
14 years 11 months ago
1998
In this paper, we present a probabilistic simulation technique to estimate the power consumption of a cmos circuit under a general delay model. This technique is based on the noti...
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JOLLI
2002
14 years 11 months ago
2002
In this paper we suggest adding to predicate modal and temporal logic a locality predicate W which gives names to worlds (or time points). We also study an equal time predicate D(x...