479 search results - page 79 / 96 » A clustering technique to optimize hardware software synchro... |
IPPS
2000
IEEE
15 years 4 months ago
2000
IEEE
As the speed gap between CPU and memory widens, memory hierarchy has become the primary factor limiting program performance. Until now, the principal focus of hardware and softwar...
123
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LCTRTS
1999
Springer
15 years 4 months ago
1999
Springer
A Zero Overhead Loop Buffer (ZOLB) is an architectural feature that is commonly found in DSP processors. This buffer can be viewed as a compiler managed cache that contains a sequ...
IEEEINTERACT
2003
IEEE
15 years 5 months ago
2003
IEEE
This paper introduces a method for improving program run-time performance by gathering work in an application and executing it efficiently in an integrated thread. Our methods ext...
PPOPP
2010
ACM
15 years 6 months ago
2010
ACM
To fully exploit multicore processors, applications are expected to provide a large degree of thread-level parallelism. While adequate for low core counts and their typical worklo...
119
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FMSD
2007
14 years 11 months ago
2007
Symbolic techniques based on Binary Decision Diagrams (BDDs) are widely employed for reasoning about temporal properties of hardware circuits and synchronous controllers. However, ...