88 search results - page 12 / 18 » A code-generator generator for multi-output instructions |
88
Voted
DATE
2008
IEEE
15 years 4 months ago
2008
IEEE
This paper presents a novel cycle-approximate performance estimation technique for automatically generated transaction level models (TLMs) for heterogeneous multicore designs. The...
VLSID
2005
IEEE
15 years 10 months ago
2005
IEEE
An Application Specific Instruction Set Processor (ASIP) exploits special characteristics of the given application(s) to meet the desired performance, cost and power requirements....
78
Voted
LCPC
2004
Springer
15 years 2 months ago
2004
Springer
Abstract. Branch predictors are associated with critical design issues for nowadays instruction greedy processors. We study two important domains where the optimization of decision...
IEEEPACT
2002
IEEE
15 years 2 months ago
2002
IEEE
This paper presents a new modulo scheduling algorithm for clustered microarchitectures. The main feature of the proposed scheme is that the assignment of instructions to clusters ...
108
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ASPLOS
2012
ACM
13 years 5 months ago
2012
ACM
Dynamic binary translation (DBT) is a powerful technique that enables fine-grained monitoring and manipulation of an existing program binary. At the user level, it has been emplo...