88 search results - page 8 / 18 » A code-generator generator for multi-output instructions |
CASES
2010
ACM
14 years 7 months ago
2010
ACM
We present a fine-grain dynamic instruction placement algorithm for small L0 scratch-pad memories (spms), whose unit of transfer can be an individual instruction. Our algorithm ca...
PLDI
1995
ACM
15 years 1 months ago
1995
ACM
Traditional list schedulers order instructions based on an optimistic estimate of the load latency imposed by the hardware and therefore cannot respond to variations in memory lat...
DAC
1995
ACM
15 years 1 months ago
1995
ACM
High-level synthesis (HLS) has been successfully targeted towards the digital signal processing (DSP) domain. Both application-speci c integrated circuits (ASICs) and application-...
FDL
2007
IEEE
15 years 1 months ago
2007
IEEE
Functional validation of microprocessors is growing in complexity in current and future microprocessors. The informal specification document from which the various collaterals are ...
CGO
2007
IEEE
15 years 3 months ago
2007
IEEE
The increasing complexity of hardware features for recent processors makes high performance code generation very challenging. In particular, several optimization targets have to b...