88 search results - page 9 / 18 » A code-generator generator for multi-output instructions |
71
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LCPC
2001
Springer
15 years 1 months ago
2001
Springer
Abstract. We describe the structure of a compilation system that generates code for processor architectures supporting both explicit and implicit parallel threads. Such architectur...
LCTRTS
2010
Springer
15 years 4 months ago
2010
Springer
A large number of embedded systems include 8-bit microcontrollers for their energy efficiency and low cost. Multi-bank memory architecture is commonly applied in 8-bit microcontr...
102
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MICRO
2003
IEEE
15 years 2 months ago
2003
IEEE
A virtual instruction set architecture (V-ISA) implemented via a processor-specific software translation layer can provide great flexibility to processor designers. Recent examp...
91
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HPCC
2009
Springer
15 years 2 months ago
2009
Springer
Usual cache optimisation techniques for high performance computing are difficult to apply in embedded VLIW applications. First, embedded applications are not always well structur...
PLDI
2005
ACM
15 years 3 months ago
2005
ACM
Code placement techniques have traditionally improved instruction fetch bandwidth by increasing instruction locality and decreasing the number of taken branches. However, traditio...