1855 search results - page 280 / 371 » A coding theorem for distributed computation |
136
Voted
ICS
1999
Tsinghua U.
15 years 8 months ago
1999
Tsinghua U.
Instruction scheduling is an important compiler technique for exploiting more instruction-level parallelism (ILP) in high-performance microprocessors, and in this paper, we study ...
134
Voted
ICS
1999
Tsinghua U.
15 years 8 months ago
1999
Tsinghua U.
Hydra is a chip multiprocessor (CMP) with integrated support for thread-level speculation. Thread-level speculation provides a way to parallelize sequential programs without the n...
144
Voted
HPCA
1998
IEEE
15 years 8 months ago
1998
IEEE
Most of the prediction mechanisms predict a single path to continue the execution on a branch. Alternatively, we may exploit parallelism from either possible paths of a branch, di...
134
Voted
HPCA
1998
IEEE
15 years 8 months ago
1998
IEEE
As we look to the future, and the prospect of a billion transistors on a chip, it seems inevitable that microprocessors will exploit having multiple parallel threads. To achieve t...
126
Voted
IEEEPACT
1998
IEEE
15 years 8 months ago
1998
IEEE
Register coalescing is used, as part of register allocation, to reduce the number of register copies. Developing efficient register coalescing heuristics is particularly important ...