38 search results - page 4 / 8 » A compiler-directed data prefetching scheme for chip multipr... |
IEEEPACT
2009
IEEE
15 years 6 months ago
2009
IEEE
Abstract—This paper proposes a new software-oriented approach for managing the distributed shared L2 caches of a chip multiprocessor (CMP) for latency-oriented multithreaded appl...
HIPEAC
2009
Springer
15 years 6 months ago
2009
Springer
Process variations, which lead to timing and power variations across identically-designed components, have been identified as one of the key future design challenges by the semico...
142
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HIPEAC
2011
Springer
13 years 11 months ago
2011
Springer
In chip multiprocessors (CMPs), data accesslatency dependson the memory hierarchy organization, the on-chip interconnect (NoC), and the running workload. Reducing data access late...
119
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DSN
2011
IEEE
13 years 11 months ago
2011
IEEE
—Aggressive technology scaling causes chip multiprocessors increasingly error-prone. Core-level faulttolerant approaches bind two cores to implement redundant execution and error...
103
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ISCA
2006
IEEE
15 years 5 months ago
2006
IEEE
This paper presents CMP Cooperative Caching, a unified framework to manage a CMP’s aggregate on-chip cache resources. Cooperative caching combines the strengths of private and ...