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MICRO
2007
IEEE
129views Hardware» more  MICRO 2007»
15 years 3 months ago
A Framework for Coarse-Grain Optimizations in the On-Chip Memory Hierarchy
Current on-chip block-centric memory hierarchies exploit access patterns at the fine-grain scale of small blocks. Several recently proposed techniques for coherence traffic reduct...
Jason Zebchuk, Elham Safi, Andreas Moshovos
HPCA
1998
IEEE
15 years 1 months ago
The Potential for Using Thread-Level Data Speculation to Facilitate Automatic Parallelization
As we look to the future, and the prospect of a billion transistors on a chip, it seems inevitable that microprocessors will exploit having multiple parallel threads. To achieve t...
J. Gregory Steffan, Todd C. Mowry
90
Voted
EUROSYS
2007
ACM
15 years 6 months ago
Thread clustering: sharing-aware scheduling on SMP-CMP-SMT multiprocessors
The major chip manufacturers have all introduced chip multiprocessing (CMP) and simultaneous multithreading (SMT) technology into their processing units. As a result, even low-end...
David K. Tam, Reza Azimi, Michael Stumm
69
Voted
PLDI
2010
ACM
15 years 2 months ago
Software data spreading: leveraging distributed caches to improve single thread performance
Single thread performance remains an important consideration even for multicore, multiprocessor systems. As a result, techniques for improving single thread performance using mult...
Md Kamruzzaman, Steven Swanson, Dean M. Tullsen
TC
2010
14 years 8 months ago
PERFECTORY: A Fault-Tolerant Directory Memory Architecture
—The number of CPUs in chip multiprocessors is growing at the Moore’s Law rate, due to continued technology advances. However, new technologies pose serious reliability challen...
Hyunjin Lee, Sangyeun Cho, Bruce R. Childers