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FCCM
2011
IEEE
220views VLSI» more  FCCM 2011»
14 years 2 months ago
Reducing the Energy Cost of Irregular Code Bases in Soft Processor Systems
— This paper describes an architecture and FPGA synthesis toolchain for building specialized, energy-saving coprocessors called Irregular Code Energy Reducers (ICERs) for a wide ...
Manish Arora, Jack Sampson, Nathan Goulding-Hotta,...
LCTRTS
2007
Springer
15 years 5 months ago
Combining source-to-source transformations and processor instruction set extensions for the automated design-space exploration o
Industry’s demand for flexible embedded solutions providing high performance and short time-to-market has led to the development of configurable and extensible processors. The...
Richard Vincent Bennett, Alastair Colin Murray, Bj...
92
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CASES
2008
ACM
15 years 1 months ago
StageNetSlice: a reconfigurable microarchitecture building block for resilient CMP systems
Although CMOS feature size scaling has been the source of dramatic performance gains, it has lead to mounting reliability concerns due to increasing power densities and on-chip te...
Shantanu Gupta, Shuguang Feng, Amin Ansari, Jason ...
ISPASS
2010
IEEE
15 years 6 months ago
Cache contention and application performance prediction for multi-core systems
—The ongoing move to chip multiprocessors (CMPs) permits greater sharing of last-level cache by processor cores but this sharing aggravates the cache contention problem, potentia...
Chi Xu, Xi Chen, Robert P. Dick, Zhuoqing Morley M...
ICMCS
2007
IEEE
94views Multimedia» more  ICMCS 2007»
15 years 5 months ago
Interoperability Issues in DRM and DMP Solutions
This paper presents an ongoing Digital Right Management (DRM) standard: Digital Media Project (DMP), which is active as an interoperable DRM solution in recent three years. We sta...
Xiaofan Chen, Tiejun Huang