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HPCA
2005
IEEE
16 years 5 days ago
Effective Instruction Prefetching in Chip Multiprocessors for Modern Commercial Applications
In this paper, we study the instruction cache miss behavior of four modern commercial applications (a database workload, TPC-W, SPECjAppServer2002 and SPECweb99). These applicatio...
Lawrence Spracklen, Yuan Chou, Santosh G. Abraham
HPCA
2004
IEEE
16 years 5 days ago
Signature Buffer: Bridging Performance Gap between Registers and Caches
Data communications between producer instructions and consumer instructions through memory incur extra delays that degrade processor performance. In this paper, we introduce a new...
Lu Peng, Jih-Kwon Peir, Konrad Lai
ICSE
2008
IEEE-ACM
15 years 12 months ago
CCVisu: automatic visual software decomposition
Understanding the structure of large existing (and evolving) software systems is a major challenge for software engineers. In reverse engineering, we aim to compute, for a given s...
Dirk Beyer
ITNG
2008
IEEE
15 years 6 months ago
Parallel FFT Algorithms on Network-on-Chips
This paper presents several parallel FFT algorithms with different degree of communication overhead for multiprocessors in Network-on-Chip(NoC) environment. Three different method...
Jun Ho Bahn, Jungsook Yang, Nader Bagherzadeh
ICDCSW
2003
IEEE
15 years 5 months ago
Gateway: A Message Hub with Store-and-Forward Messaging in Mobile Networks
To obtain good performance in messaging over mobile networks, we have developed a Gateway. Gateway is a message hub that transmits information using store-and-forward messaging an...
Eiko Yoneki, Jean Bacon