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» A datapath synthesis system for the reconfigurable datapath ...
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ICCAD
1993
IEEE
97views Hardware» more  ICCAD 1993»
15 years 1 months ago
High level synthesis for reconfigurable datapath structures
Lisa M. Guerra, Miodrag Potkonjak, Jan M. Rabaey
EURODAC
1995
IEEE
127views VHDL» more  EURODAC 1995»
15 years 1 months ago
Layout synthesis for datapath designs
DPLAYOUT is a layout synthesis tool for bit-sliced datapath designs targeting standard-cell libraries. We developed fast and efficient heuristics for placing the cells in a bit-s...
Naveen Buddi, Malgorzata Chrzanowska-Jeske, Charle...
DAC
2000
ACM
15 years 10 months ago
Hardware-software co-design of embedded reconfigurable architectures
In this paper we describe a new hardware/software partitioning approach for embedded reconfigurable architectures consisting of a general-purpose processor (CPU), a dynamically re...
Yanbing Li, Tim Callahan, Ervan Darnell, Randolph ...
ISSS
2002
IEEE
95views Hardware» more  ISSS 2002»
15 years 2 months ago
Datapath Merging and Interconnection Sharing for Reconfigurable Architectures
Guido Araujo, Sharad Malik, Zhining Huang, Nahri M...
ISSS
1999
IEEE
168views Hardware» more  ISSS 1999»
15 years 1 months ago
Automatic Architectural Synthesis of VLIW and EPIC Processors
This paper describes a mechanism for automatic design and synthesis of very long instruction word (VLIW), and its generalization, explicitly parallel instruction computing rocesso...
Shail Aditya, B. Ramakrishna Rau, Vinod Kathail