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» A decoupled KILO-instruction processor
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JUCS
2000
120views more  JUCS 2000»
14 years 9 months ago
Execution and Cache Performance of the Scheduled Dataflow Architecture
: This paper presents an evaluation of our Scheduled Dataflow (SDF) Processor. Recent focus in the field of new processor architectures is mainly on VLIW (e.g. IA-64), superscalar ...
Krishna M. Kavi, Joseph Arul, Roberto Giorgi
ARCS
2006
Springer
15 years 1 months ago
Scalable and Partitionable Asynchronous Arbiter for Micro-threaded Chip Multiprocessors
Abstract. This paper presents a scalable and partitionable asynchronous bus arbiter for use with chip multiprocessors (CMP) and its corresponding pre-layout simulation results usin...
Nabil Hasasneh, Ian Bell, Chris R. Jesshope
DSD
2007
IEEE
142views Hardware» more  DSD 2007»
15 years 4 months ago
Decoupling of Computation and Communication with a Communication Assist
Abstract. In an embedded multiprocessor system the minimum throughput and maximum latency of real-time applications are usually derived given the worst-case execution time of the s...
Arno Moonen, Marco Bekooij, Rene van den Berg, Jef...
DSN
2009
IEEE
15 years 4 months ago
Decoupling Dynamic Information Flow Tracking with a dedicated coprocessor
Dynamic Information Flow Tracking (DIFT) is a promising security technique. With hardware support, DIFT prevents a wide range of attacks on vulnerable software with minimal perfor...
Hari Kannan, Michael Dalton, Christos Kozyrakis
JSA
2007
152views more  JSA 2007»
14 years 9 months ago
Asynchronous arbiter for micro-threaded chip multiprocessors
This paper presents a scalable and partitionable asynchronous bus arbiter for use with chip multiprocessors (CMP) and its corresponding pre-layout simulation results using VHDL. T...
Nabil Hasasneh, Ian Bell, Chris R. Jesshope