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» A decoupled KILO-instruction processor
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MICRO
2005
IEEE
136views Hardware» more  MICRO 2005»
15 years 6 months ago
Automatic Thread Extraction with Decoupled Software Pipelining
Until recently, a steadily rising clock rate and other uniprocessor microarchitectural improvements could be relied upon to consistently deliver increasing performance for a wide ...
Guilherme Ottoni, Ram Rangan, Adam Stoler, David I...
IEEEPACT
2009
IEEE
15 years 7 months ago
DDCache: Decoupled and Delegable Cache Data and Metadata
Abstract—In order to harness the full compute power of manycore processors, future designs must focus on effective utilization of on-chip cache and bandwidth resources. In this p...
Hemayet Hossain, Sandhya Dwarkadas, Michael C. Hua...
ICCD
2006
IEEE
183views Hardware» more  ICCD 2006»
15 years 10 months ago
An Active Decoupling Capacitance Circuit for Inductive Noise Suppression in Power Supply Networks
The placement of on-die decoupling capacitors (decap) between the power and ground supply grids has become a common practice in high performance processor designs. In this paper, ...
Sanjay Pant, David Blaauw
HPCA
1999
IEEE
15 years 5 months ago
The Synergy of Multithreading and Access/Execute Decoupling
This work presents and evaluates a novel processor microarchitecture which combines two paradigms: access/ execute decoupling and simultaneous multithreading. We investigate how b...
Joan-Manuel Parcerisa, Antonio González
IPPS
2009
IEEE
15 years 7 months ago
Exploiting DMA to enable non-blocking execution in Decoupled Threaded Architecture
DTA (Decoupled Threaded Architecture) is designed to exploit fine/medium grained Thread Level Parallelism (TLP) by using a distributed hardware scheduling unit and relying on exi...
Roberto Giorgi, Zdravko Popovic, Nikola Puzovic