102 search results - page 11 / 21 » A design platform for 90-nm leakage reduction techniques |
FPL
2010
Springer
14 years 10 months ago
2010
Springer
The paper describes application of the clock-gating techniques, often used in ASIC designs, to the field of FPGAbased systems. The clock-gating techniques are used to reduce the to...
73
Voted
ISQED
2005
IEEE
15 years 6 months ago
2005
IEEE
Leakage power has become one of the most critical design concerns for the system-level chip designer. Multi-threshold techniques have been used to reduce runtime leakage power wit...
97
Voted
DATE
2009
IEEE
15 years 7 months ago
2009
IEEE
— Clock-gating and power-gating have proven to be very effective solutions for reducing dynamic and static power, respectively. The two techniques may be coupled in such a way th...
98
Voted
ASPDAC
2009
ACM
15 years 6 months ago
2009
ACM
— Negative Bias Temperature Instability (NBTI) in PMOS transistors has become a major reliability concern in present-day digital circuit design. Further, with the recent usage of...
DATE
2010
IEEE
15 years 2 months ago
2010
IEEE
An increasing concern amongst designers and integrators of military and defense-related systems is the underlying security of the individual microprocessor components that make up ...