Sciweavers

182 search results - page 1 / 37
» A distributed processor state management architecture for la...
Sort
View
MICRO
2008
IEEE
107views Hardware» more  MICRO 2008»
14 years 20 days ago
A distributed processor state management architecture for large-window processors
— Processor architectures with large instruction windows have been proposed to expose more instruction-level parallelism (ILP) and increase performance. Some of the proposed arch...
Isidro Gonzalez, Marco Galluzzi, Alexander V. Veid...
DATE
2009
IEEE
129views Hardware» more  DATE 2009»
14 years 1 months ago
Distributed peak power management for many-core architectures
Recently proposed techniques for peak power management [5] involve centralized decision-making and assume quick evaluation of the various power management states. These techniques...
John Sartori, Rakesh Kumar
HIPC
2009
Springer
13 years 4 months ago
Three scalable approaches to improving many-core throughput for a given peak power budget
Recently proposed techniques for peak power management [18] involve centralized decisionmaking and assume quick evaluation of the various power management states. These techniques...
John Sartori, Rakesh Kumar
DAC
2006
ACM
14 years 7 days ago
Hierarchical power distribution and power management scheme for a single chip mobile processor
A hierarchical power distribution methodology that enables more than dozen power domains in a chip and a power management scheme using 20 power domains are described. This method ...
Toshihiro Hattori, Takahiro Irita, Masayuki Ito, E...
HPCA
2006
IEEE
14 years 6 months ago
An approach for implementing efficient superscalar CISC processors
An integrated, hardware / software co-designed CISC processor is proposed and analyzed. The objectives are high performance and reduced complexity. Although the x86 ISA is targete...
Shiliang Hu, Ilhyun Kim, Mikko H. Lipasti, James E...