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ISCA
2002
IEEE
95views Hardware» more  ISCA 2002»
15 years 2 months ago
An Instruction Set and Microarchitecture for Instruction Level Distributed Processing
An instruction set architecture (ISA) suitable for future microprocessor design constraints is proposed. The ISA has hierarchical register files with a small number of accumulator...
Ho-Seop Kim, James E. Smith
SIGMOD
2002
ACM
187views Database» more  SIGMOD 2002»
15 years 10 months ago
A Conceptual Architecture for Semantic Web Enabled Web Services
Semantic Web Enabled Web Services (SWWS) will transform the web from a static collection of information into a distributed device of computation on the basis of Semantic Web techn...
Christoph Bussler, Dieter Fensel, Alexander Maedch...
PVLDB
2008
96views more  PVLDB 2008»
14 years 9 months ago
H-store: a high-performance, distributed main memory transaction processing system
Our previous work has shown that architectural and application shifts have resulted in modern OLTP databases increasingly falling short of optimal performance [10]. In particular,...
Robert Kallman, Hideaki Kimura, Jonathan Natkins, ...
IPPS
2005
IEEE
15 years 3 months ago
Configuration Steering for a Reconfigurable Superscalar Processor
An architecture for a reconfigurable superscalar processor is described in which some of its execution units are implemented in reconfigurable hardware. The overall configuration ...
Brian F. Veale, John K. Antonio, Monte P. Tull
OTM
2005
Springer
15 years 3 months ago
An Hybrid Intermediation Architectural Approach for Integrating Cross-Organizational Services
Nowadays, workflow research has shifted from fundamentals of workflow modelling and enactment towards improvement of the workflow modelling lifecycle and integration of workflow en...
Giannis Verginadis, Panagiotis Gouvas, Gregoris Me...