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DATE
2008
IEEE
145views Hardware» more  DATE 2008»
15 years 3 months ago
Minimizing Virtual Channel Buffer for Routers in On-chip Communication Architectures
We present a novel methodology for design space exploration using a two-steps scheme to optimize the number of virtual channel buffers (buffers take the premier share of the route...
Mohammad Abdullah Al Faruque, Jörg Henkel
HPDC
2002
IEEE
15 years 2 months ago
Dynamic Right-Sizing in FTP (drsFTP): Enhancing Grid Performance in User-Space
With the advent of computational grids, networking performance over the wide-area network (WAN) has become a critical component in the grid infrastructure. Unfortunately, many hig...
Mark K. Gardner, Wu-chun Feng, Mike Fisk
ARC
2010
Springer
138views Hardware» more  ARC 2010»
15 years 23 days ago
Space and Time Sharing of Reconfigurable Hardware for Accelerated Parallel Processing
High-Performance Reconfigurable Computers (HPRCs) are parallel machines consisting of FPGAs and microprocessors, with the FPGAs used as co-processors. The execution of parallel app...
Esam El-Araby, Vikram K. Narayana, Tarek A. El-Gha...
IOPADS
1997
152views more  IOPADS 1997»
14 years 10 months ago
Competitive Parallel Disk Prefetching and Buffer Management
We provide a competitive analysis framework for online prefetching and buffer management algorithms in parallel I/O systems, using a read-once model of block references. This has ...
Rakesh D. Barve, Mahesh Kallahalla, Peter J. Varma...
IEEEPACT
2009
IEEE
14 years 7 months ago
Cache Sharing Management for Performance Fairness in Chip Multiprocessors
Resource sharing can cause unfair and unpredictable performance of concurrently executing applications in Chip-Multiprocessors (CMP). The shared last-level cache is one of the mos...
Xing Zhou, Wenguang Chen, Weimin Zheng