24 search results - page 2 / 5 » A dynamically reconfigurable cache for multithreaded process... |
MICRO
1998
IEEE
15 years 3 months ago
1998
IEEE
We present an architecture that features dynamic multithreading execution of a single program. Threads are created automatically by hardware at procedure and loop boundaries and e...
116
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ISHPC
2003
Springer
15 years 4 months ago
2003
Springer
Simultaneous multithreaded processors use shared on-chip caches, which yield better cost-performance ratios. Sharing a cache between simultaneously executing threads causes excessi...
MICRO
2000
IEEE
15 years 3 months ago
2000
IEEE
Conventional microarchitectures choose a single memory hierarchy design point targeted at the average application. In this paper, we propose a cache and TLB layout and design that...
133
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ISPASS
2005
IEEE
15 years 5 months ago
2005
IEEE
Today’s general-purpose processors are increasingly using multithreading in order to better leverage the additional on-chip real estate available with each technology generation...
MICRO
2005
IEEE
15 years 5 months ago
2005
IEEE
Data prefetching via helper threading has been extensively investigated on Simultaneous MultiThreading (SMT) or Virtual Multi-Threading (VMT) architectures. Although reportedly la...