2297 search results - page 27 / 460 » A fast APRIORI implementation |
FPL
2003
Springer
15 years 3 months ago
2003
Springer
This paper describes the implementation of the L3 maze routing accelerator in an FPGA. L3 supports fast single-layer and multi-layer routing, preferential routing, and rip-up-and-r...
103
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TIM
2010
14 years 5 months ago
2010
In the last few years, the growing complexity of the electrical power networks, mainly due to the increased use of electronic converters together with the requirements of a higher ...
108
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AICT
2006
IEEE
15 years 4 months ago
2006
IEEE
— Resilient Routing Layers (RRL) and Multiple Routing Configurations (MRC) have been proposed as methods to achieve fast recovery from router and link failures in connectionless...
ASPDAC
2006
ACM
15 years 4 months ago
2006
ACM
– We propose improvement of the new architecture of digital FM demodulator. This work enhances signal quality, system clock frequency, and superior than well known PLL technique ...
91
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EH
2003
IEEE
15 years 3 months ago
2003
IEEE
Reconfigurable hardware devices make it possible to change the topology of electronic circuits at runtime. Using reconfigurable devices as a platform for Evolvable hardware (EHW) ...