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DAC
2006
ACM
15 years 11 months ago
Early cutpoint insertion for high-level software vs. RTL formal combinational equivalence verification
Ever-growing complexity is forcing design to move above RTL. For example, golden functional models are being written as clearly as possible in software and not optimized or intend...
Xiushan Feng, Alan J. Hu
VLSID
2003
IEEE
180views VLSI» more  VLSID 2003»
15 years 10 months ago
Automating Formal Modular Verification of Asynchronous Real-Time Embedded Systems
Most verification tools and methodologies such as model checking, equivalence checking, hardware verification, software verification, and hardware-software coverification often fl...
Pao-Ann Hsiung, Shu-Yu Cheng
ASWEC
1998
IEEE
15 years 2 months ago
Supplementing Process-Oriented with Structure-Oriented Design Explanation within Formal Object Oriented Method
This paper reports the results from an action research project which studies the benefits of documenting the evolution and the rationale for the evolution of a requirements specif...
LeMai Nguyen, Paul A. Swatman, Graeme G. Shanks
SACMAT
2009
ACM
15 years 2 months ago
A formal framework to elicit roles with business meaning in RBAC systems
The role-based access control (RBAC) model has proven to be cost effective to reduce the complexity and costs of access permission management. To maximize the advantages offered...
Alessandro Colantonio, Roberto Di Pietro, Alberto ...
DFG
2004
Springer
15 years 1 months ago
Modeling and Formal Verification of Production Automation Systems
This paper presents the real-time model checker RAVEN and related theoretical background. RAVEN augments the efficiency of traditional symbolic model checking with possibilities to...
Jürgen Ruf, Roland J. Weiss, Thomas Kropf, Wo...