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IPPS
1998
IEEE
13 years 10 months ago
Synthesis of a Systolic Array Genetic Algorithm
The paper presents the design of a hardware genetic algorithm which uses a pipeline of systolic arrays. Demostrated is the design methodology, where a simple genetic algorithm exp...
Graham M. Megson, I. M. Bland
IKE
2004
13 years 7 months ago
Agent-Based Optimization of Business Functions Using Coevolutionary Algorithms
This paper presents one target of the Evo-business project (2003-2005, conducted at University of Luxembourg) which aims at applying evolutionary algorithms (and more precisely lo...
Grégoire Danoy, Pascal Bouvry, Franciszek S...
ICES
2003
Springer
151views Hardware» more  ICES 2003»
13 years 11 months ago
Using Genetic Programming and High Level Synthesis to Design Optimized Datapath
This paper presents a methodology to design optimized electronic systems from high abstraction level descriptions. The methodology uses Genetic Programming in addition to high-leve...
Sérgio G. Araújo, Antônio C. M...
VEE
2012
ACM
187views Virtualization» more  VEE 2012»
12 years 1 months ago
DDGacc: boosting dynamic DDG-based binary optimizations through specialized hardware support
Dynamic Binary Translators (DBT) and Dynamic Binary Optimization (DBO) by software are used widely for several reasons including performance, design simplification and virtualiza...
Demos Pavlou, Enric Gibert, Fernando Latorre, Anto...
ICES
2010
Springer
106views Hardware» more  ICES 2010»
13 years 4 months ago
The Use of Genetic Algorithm to Reduce Power Consumption during Test Application
Abstract. In this paper it is demonstrated how two issues from the area of testing electronic components can be merged and solved by means of a genetic algorithm. The two issues ar...
Jaroslav Skarvada, Zdenek Kotásek, Josef St...