70 search results - page 13 / 14 » A hardware software partitioning algorithm for pipelined ins... |
DATE
2003
IEEE
13 years 11 months ago
2003
IEEE
Smart cards are vulnerable to both invasive and non-invasive attacks. Specifically, non-invasive attacks using power and timing measurements to extract the cryptographic key has d...
DAC
1999
ACM
13 years 10 months ago
1999
ACM
We present our practical experience in the modeling and integration of cycle/phase-accurate instruction set architecture (ISA) models of digital signal processors (DSPs) with othe...
ISCA
2006
IEEE
13 years 6 months ago
2006
IEEE
Conventional relaxed memory ordering techniques follow a proactive model: at a synchronization point, a processor makes its own updates to memory available to other processors by ...
CODES
2008
IEEE
14 years 21 days ago
2008
IEEE
The heterogeneity of modern MPSoC architectures, coupled with the increasing complexity of the applications mapped onto them has recently led to a lot of interest in hybrid perfor...
CODES
2001
IEEE
13 years 10 months ago
2001
IEEE
Most research to date on energy minimization in DSP processors has focuses on hardware solution. This paper examines the software-based factors affecting performance and energy co...