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PPL
2008
185views more  PPL 2008»
14 years 11 months ago
On Design and Application Mapping of a Network-on-Chip(NoC) Architecture
As the number of integrated IP cores in the current System-on-Chips (SoCs) keeps increasing, communication requirements among cores can not be sufficiently satisfied using either ...
Jun Ho Bahn, Seung Eun Lee, Yoon Seok Yang, Jungso...
ICCD
2000
IEEE
107views Hardware» more  ICCD 2000»
15 years 8 months ago
Architectural Impact of Secure Socket Layer on Internet Servers
Secure socket layer SSL is the most popular protocol used in the Internet for facilitating secure communications through authentication, encryption, and decryption. Although the...
Krishna Kant, Ravishankar K. Iyer, Prasant Mohapat...
GLOBECOM
2006
IEEE
15 years 5 months ago
Scalable Layer-2/Layer-3 Multistage Switching Architectures for Software Routers
Abstract— Software routers are becoming an important alternative to proprietary and expensive network devices, because they exploit the economy of scale of the PC market and open...
Andrea Bianco, Jorge M. Finochietto, Giulio Galant...
HPCA
2009
IEEE
16 years 5 days ago
Design and evaluation of a hierarchical on-chip interconnect for next-generation CMPs
Performance and power consumption of an on-chip interconnect that forms the backbone of Chip Multiprocessors (CMPs), are directly influenced by the underlying network topology. Bo...
Reetuparna Das, Soumya Eachempati, Asit K. Mishra,...
ICCAD
2004
IEEE
114views Hardware» more  ICCAD 2004»
15 years 8 months ago
High-level synthesis using computation-unit integrated memories
Abstract— High-level synthesis (HLS) of memory-intensive applications has featured several innovations in terms of enhancements made to the basic memory organization and data lay...
Chao Huang, Srivaths Ravi, Anand Raghunathan, Nira...