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IPPS
2009
IEEE
15 years 5 months ago
Optimizing assignment of threads to SPEs on the cell BE processor
The Cell is a heterogeneous multicore processor that has attracted much attention in the HPC community. The bulk of the computational workload on the Cell processor is carried by ...
C. Devi Sudheer, T. Nagaraju, Pallav K. Baruah, As...
ASPLOS
1998
ACM
15 years 3 months ago
A Cost-Effective, High-Bandwidth Storage Architecture
This paper describes the Network-Attached Secure Disk (NASD) storage architecture, prototype implementations of NASD drives, array management for our architecture, and three files...
Garth A. Gibson, David Nagle, Khalil Amiri, Jeff B...
TMC
2010
85views more  TMC 2010»
14 years 9 months ago
Juggler: Virtual Networks for Fun and Profit
—There are many situations in which an additional network interface—or two—can provide benefits to a mobile user. Additional interfaces can support parallelism in network flo...
Anthony J. Nicholson, Scott Wolchok, Brian D. Nobl...
CCGRID
2001
IEEE
15 years 2 months ago
xBSP: An Efficient BSP Implementation for clan
Virtual Interface Architecture(VIA) is a light-weight protocol for protected user-level zero-copy communication. In spite of high performance of VIA, the previous MPI implementati...
Yang-Suk Kee, Soonhoi Ha
ISCA
2011
IEEE
269views Hardware» more  ISCA 2011»
14 years 2 months ago
Crafting a usable microkernel, processor, and I/O system with strict and provable information flow security
High assurance systems used in avionics, medical implants, and cryptographic devices often rely on a small trusted base of hardware and software to manage the rest of the system. ...
Mohit Tiwari, Jason Oberg, Xun Li 0001, Jonathan V...