1 The increasing test data volume needed to test core-based System-on-Chip contributes to long test application times (TAT) and huge automatic test equipment (ATE) memory requireme...
Anders Larsson, Erik Larsson, Petru Eles, Zebo Pen...
The increasing levels of system integration in Multi-Processor System-on-Chips (MPSoCs) emphasize the need for new design flows for efficient mapping of multi-task applications o...
High-level synthesis (HLS) has been successfully targeted towards the digital signal processing (DSP) domain. Both application-specic integrated circuits (ASICs) and application-...
Abstract. Interleaved planning and scheduling employs the idea of extending partial plans by regularly heeding to the scheduling constraints during search. One of the techniques us...
—We consider the problem of joint routing, scheduling and power control in multi-hop wireless networks. We use a linear relation between link capacity and signal to interference ...
Javad Kazemitabar, Vahid Tabatabaee, Hamid Jafarkh...