Sciweavers

106 search results - page 10 / 22
» A logic you can count on
Sort
View
90
Voted
ISMVL
1998
IEEE
113views Hardware» more  ISMVL 1998»
15 years 1 months ago
Look-up Tables (LUTs) for Multiple-Valued, Combinational Logic
The use of Look-Up Tables (LUTs) is extended from binary to multiple-valued logic (MVL) circuits. A multiplevalued LUT can be implemented using both current-mode and voltage-mode ...
Ali Sheikholeslami, R. Yoshimura, P. Glenn Gulak
68
Voted
FPGA
2008
ACM
131views FPGA» more  FPGA 2008»
14 years 11 months ago
WireMap: FPGA technology mapping for improved routability
This paper presents a new technology mapper, WireMap. The mapper uses an edge flow heuristic to improve the routability of a mapped design. The heuristic is applied during the ite...
Stephen Jang, Billy Chan, Kevin Chung, Alan Mishch...
GG
2004
Springer
15 years 3 months ago
Representing First-Order Logic Using Graphs
We show how edge-labelled graphs can be used to represent first-order logic formulae. This gives rise to recursively nested structures, in which each level of nesting corresponds ...
Arend Rensink
71
Voted
ICCAD
2008
IEEE
153views Hardware» more  ICCAD 2008»
15 years 6 months ago
Boolean factoring and decomposition of logic networks
This paper presents new methods for restructuring logic networks based on fast Boolean techniques. The basis for these are 1) a cut based view of a logic network, 2) exploiting th...
Alan Mishchenko, Robert K. Brayton, Satrajit Chatt...
MJ
2008
58views more  MJ 2008»
14 years 9 months ago
Using multi-threshold threshold gates in RTD-based logic design: A case study
Abstract - The basic building blocks for Resonant Tunnelling Diode (RTD) logic circuits are Threshold Gates (TGs) instead of the conventional Boolean gates (AND, OR, NAND, NOR) due...
Héctor Pettenghi, Maria J. Avedillo, Jos&ea...