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136
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IESS
2007
Springer
165views Hardware» more  IESS 2007»
15 years 8 months ago
Data Reuse Driven Memory and Network-On-Chip Co-Synthesis
NoCs present a possible communication infrastructure solution to deal with increased design complexity and shrinking time-to-market. The communication infrastructure is a signific...
Ilya Issenin, Nikil Dutt
59
Voted
DATE
2006
IEEE
70views Hardware» more  DATE 2006»
15 years 7 months ago
A low complexity heuristic for design of custom network-on-chip architectures
Krishnan Srinivasan, Karam S. Chatha
146
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INTEGRATION
2008
183views more  INTEGRATION 2008»
15 years 1 months ago
Network-on-Chip design and synthesis outlook
With the growing complexity in consumer embedded products, new tendencies forecast heterogeneous Multi-Processor SystemsOn-Chip (MPSoCs) consisting of complex integrated component...
David Atienza, Federico Angiolini, Srinivasan Mura...
ICCD
2004
IEEE
122views Hardware» more  ICCD 2004»
15 years 10 months ago
Linear Programming based Techniques for Synthesis of Network-on-Chip Architectures
Network-on-chip (NoC) has been proposed as a solution for the communication challenges of System-on-chip (SoC) design in the nanoscale regime. SoC design offers the opportunity fo...
Krishnan Srinivasan, Karam S. Chatha, Goran Konjev...
137
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CASES
2004
ACM
15 years 7 months ago
A low power architecture for embedded perception
Recognizing speech, gestures, and visual features are important interface capabilities for future embedded mobile systems. Unfortunately, the real-time performance requirements of...
Binu K. Mathew, Al Davis, Michael Parker