15 search results - page 2 / 3 » A low energy architecture for fast PN acquisition |
115
Voted
HPCA
2005
IEEE
15 years 10 months ago
2005
IEEE
A large multi-ported register file is indispensable for exploiting instruction level parallelism (ILP) in today's dynamically scheduled superscalar processors. The number of ...
87
Voted
HPCA
2005
IEEE
15 years 10 months ago
2005
IEEE
ZettaRAMTM is a new memory technology under development by ZettaCoreTM as a potential replacement for conventional DRAM. The key innovation is replacing the conventional capacitor...
ISLPED
2005
ACM
15 years 3 months ago
2005
ACM
Tuning a configurable cache subsystem to an application can greatly reduce memory hierarchy energy consumption. Previous tuning methods use a level one configurable cache only, or...
ISSS
2002
IEEE
15 years 2 months ago
2002
IEEE
Adding a small loop cache to a microprocessor has been shown to reduce average instruction fetch energy for various sets of embedded system applications. With the advent of core-b...
VLSID
2002
IEEE
15 years 10 months ago
2002
IEEE
With the projected significant growth in mobile internet and multimedia services, there is a strong demand for nextgeneration appliances capable of wireless image communication. O...